A 4T (four-transistor) SRAM (static random access memory) cell contains four transistors and two load devices (or "loads") within each memory cell. Typically, the transistors are MOSFETs (MOS field effect transistors) and the loads are polysilicon transistors that are undoped or lightly doped to provide a high electrical resistance so as to serve as an insulator. Conventionally, the loads are formed by first depositing a polysilicon film on the substrate, followed by high-energy blanket implantation using an appropriate dopant to obtain the desired resistance intended for the loads. After the blanket implantation, a photolithography technique is applied to form a polysilicon line pattern which encompasses the portion of the polysilicon film intended to be connectors. A high-density dopant implantation is then applied to the connector area (which process is often called "connector implantation") to significantly reduce its resistance. The undoped area during the second, masked, implantation remains at relatively high resistance and serves as loads between respective pairs of connectors.
The resistance of loads is determined by the amount of dopant implanted during the first, or blanket, implantation, the thickness of the polysilicon film, the width and length of the load lines, etc. Conventionally, in order to obtain high enough load resistance, the circuit design engineers have to reduce the polysilicon film thickness, increase the load length, or reduce the load width, or combinations thereof. However, as the cell size of the SRAM continues to be reduced, the conventional approach is facing serious problems. One of the major obstacles is that, due to the outdiffusion of dopants from the connector areas, the effective length of the load will be reduced to an even greater extent relative to its actual length as the actual length of the load becomes shorter. While the load resistance may be increased by reducing the width of the load, the minimum width, however, is limited by the underlying photolithography technique. Upgrading the photolithography process can be a very expensive undertaking which will require large capital investments. Thus, the inability to provide adequate load resistance under the currently existing techniques has become one of the major remaining problems in attempts to further reduce SRAM cell size.
The technique to increase the effective length of an SRAM load without increasing its physical dimension as disclosed in the present invention has not been taught or suggested in any prior art references. However, several issued patents discussed the fabrication of 4T SRAM in general. They are briefly discussed below.
U.S. Pat. No. 5,605,853 disclosed an integrated process for forming a 4T SRAM and a floating gate memory, with logic, on the same integrated circuit. One of the key elements of the '853 patent is that, through its various process elements as recited in its claims, the logic salicide and the SRAM local interconnect are formed simultaneously and that the floating memory and logic on the same substrate in which gate-to-source/drain contacts are butted contacts having reduced contact resistance. The '853 patent never discussed the need to increase the effective length of the load device.
U.S. Pat. No. 5,700,711 disclosed a method for manufacturing a load shield structure which is formed over each of the undoped or lightly doped polysilicon load devices of a 4T SRAM cell. The method includes the steps of: (1) forming a polycrystalline silicon structure over a memory cell of an SRAM device; (2) forming a load mask over the polycrystalline silicon structure covering a region where a load structure is to be formed, the load mask being patterned using a master load mask; (3) doping regions of the polycrystalline silicon structure not covered by the load mask; (4) forming a blanket dielectric layer over the SRAM device covering the polycrystalline silicon structure and other exposed surfaces of the SRAM device; and (5) forming a dummy conductor structure on the blanket dielectric layer. The purpose of the dummy conductor structure is to protect the polycrystalline silicon load resistor during subsequent processing steps. Again, the '711 patent did not teach or suggest any means to increase the effective length of the SRAM load devices.